- #AMD K10 SERIES FULL#
- #AMD K10 SERIES CODE#
AMD Puma Family 16h (2nd-gen) – the successor to Jaguar. AMD Jaguar Family 16h – the successor to Bobcat. Ontario and Zacate were the first designs which implemented it. AMD Bobcat Family 14h – a new distinct line, which is aimed in the 1 W to 10 W low power microprocessor category. Llano was the first design which implemented it. Includes CPU cores, GPU and Northbridge in the same chip. AMD Fusion Family 12h – based on the 10h/K10 design. AMD Family 11h – combined elements of K8 and K10 designs for Turion X2 Ultra / Puma mobile platform. Barcelona was the first design which implemented it. Shared Level 3 Cache, 128-bit floating point units, AMD-V Nested Paging virtualization, and HyperTransport 3.0 are introduced. AMD Family 10h (K10) – based on the K8 microarchitecture. The codename was recycled at least once until ultimately being dropped before any public mention of it. SledgeHammer was the first design which implemented it. K8 replaced the traditional front side bus with a HyperTransport communication fabric. The K8 was the first mainstream Windows-compatible 64-bit microprocessor and was released April 22, 2003. Based on the K7 but was designed around a 64-bit ISA, added an integrated memory controller, HyperTransport communication fabric, L2 cache sizes up to 1 MB (1128 KB total cache), and SSE2. AMD K8 Hammer – also known as AMD Family 0Fh. #AMD K10 SERIES FULL#
The third generation, branded as XP, introduced full support for SSE. The second generation returned to the traditional socket form factor with fully integrated L2-cache running at full speed. First generation was built with a separate L2-cache chip on a board inserted into a slot ( A) and introduced extended MMX.
AMD K7 Athlon – microarchitecture of the AMD Athlon classic and Athlon XP microprocessors. AMD K6-III Sharptooth – a further improved K6 with three levels of cache – 64 KB L1, 256 KB full-speed on-die L2, and a variable (up to 2 MB) 元. AMD K6-2 – an improved K6 with the addition of the 3DNow! SIMD instructions. The K6 was generally pin-compatible with the Intel Pentium (unlike NexGen's existing processors). AMD K6 – the K6 was not based on the K5 and was instead based on the N圆86 processor that was being designed by NexGen when that company was bought by AMD. Although the design was similar in idea to a Pentium Pro, the actual performance was more like that of a Pentium. The K5 was based on the AMD Am29k micro architecture with the addition of an x86 decoder. AMD K5 – AMD's first original x86 microarchitecture. Family field of the application, as can be seen on various screenshots on the CPU-Z Validator World Records website.īelow is a list of microarchitectures many of which have codenames associated: The Family hexadecimal identifier number can be determined for a particular processor using the freeware system profiling application CPU-Z, which shows the Family number in the Ext. #AMD K10 SERIES CODE#
(The "K10h" form that sometimes pops up is an improper hybrid of the "K" code and Family XXh identifier number.)īulldozer / Piledriver / Steamroller / Excavator In hexadecimal numbering, 0F(h) (where the h represents hexadecimal numbering) equals the decimal number 15, and 10(h) equals the decimal number 16. 10h and 0Fh refer to the main result of the CPUID x86 processor instruction. AMD now refers to the codename K8 processors as the Family 0Fh processors. AMD has not used K-nomenclature codenames in official AMD documents and press releases since the beginning of 2005, when K8 described the Athlon 64 processor family. Historically, AMD's CPU families were given a "K-number" (which originally stood for Kryptonite, an allusion to the Superman comic book character's fatal weakness) starting with their first internal x86 CPU design, the K5, to represent generational changes.
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